A modern integrated circuit memory device frequently includes one or more power-gating mechanisms that allow the power consumption for that memory device to be reduced while the memory device is not in active use. Such a memory device may, for example, include one or more pins that allow the memory device to be placed in one of several power-saving modes, such as a “light sleep” mode, a “deep sleep” mode, and a “shut-down” mode. Each of these power-saving modes utilizes sufficiently-sized power gates (e.g., metal-oxide-semiconductor field effect transistors (MOSFETs)) to progressively power down more circuitry within the memory device. In the light sleep mode, for example, just the memory device's row and column decoders may be powered down. In contrast, in the more extreme shut-down mode, all the circuitry within the memory device may be powered down including the memory's memory array and any output restoration circuitry. In the shut-down mode, all stored data is typically lost.
There is typically some delay in powering the elements within a memory device up to their fully functional status when restoring a memory device from a power-saving mode. This recovery time is frequently specified by the manufacturer and must be accounted for by means of a data processing system's firmware. Accessing a memory device when the memory device has not fully exited from a power-saving mode can result in unpredictable behavior including data loss.